library ieee;
use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity multiplier is port (

	clk : in std_logic;

	inputA, inputB : in std_logic_vector(31 downto 0);
	output : out std_logic_vector(31 downto 0);


end entity;



architecture arch of multiplier is

signal a,b std_logic_vector(31 downto 0);


component modulo
generic(n: INTEGER := 32);
port(

 input1, input2 : in STD_LOGIC_VECTOR (n-1 downto 0);
 output : out STD_LOGIC_VECTOR (n-1 downto 0)

);

end component;


begin




process
begin

	a <= inputA;
	b <= "00000000000000000000000000000000";

	L1: loop
    exit L1 when b >= inputB;
	
	
		
		a <= a rol 2;
		
		iADDER : adder port map(

			b,
			"00000000000000000000000000000010",
			b
			
		);
			
		
	
	end loop;

end process;

output <= a;

end arch;